The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology which is effected when used in a CMOS (i.e., Complementary MOS) integrated circuit having input/output interfaces of different levels, for example.
An example of a semiconductor integrated circuit device having a function to handle a plurality of signal levels is disclosed in Japanese Patent Laid-Open No. 176585/1982. According to this Laid-Open Application, a circuit constituting an electronic watch or an electronic desk computer has its operating voltage dropped to reduce the current consumption. In this case, the display signal level of a liquid crystal or the like is so much higher than the aforementioned operating voltage that level changing circuits become necessary. In order to reduce the number of these level changing circuits, the operating voltage of a RAM for storing the display data is raised according to the display signal level, and the data to be written in the RAM are written at a changed level whereas the data to be read out from the RAM have their data level dropped by a clocked inverter circuit before they are outputted.
An example of a semiconductor device, which has succeeded in reducing the influences of supply noises due to the spike current at the switching time of an output circuit by forming the output circuit supply terminals of different in-chip pads, is disclosed in Japanese Patent Laid-Open No. 264747/1986.
In Japanese Patent Laid-Open No. 199250/1982, there is disclosed another example of a semiconductor integrated circuit device which is enabled to supply power selectively to a plurality of in-chip functional blocks by dividing the power supply line to the functional blocks, thereby to reduce a rise in the design and production costs accompanying the production of the multiple kinds in a small quantity for achieving multiple functions by a single design.
In Japanese Patent Laid-Open No. 31438/1989, there is disclosed an example of a gate array device which is enabled to reduce the power supply noises or to use another supply line by providing a wiring line for a basic cell and an I/O cell to lead in the supply power.
In Japanese Patent Laid-Open No. 47843/1990, there is disclosed an example of an integrated circuit manufacturing method, by which a band-shaped metal film is formed and cut by setting positions to be electrically connected with an input/output buffer circuit portion in a manner to correspond to the leads of a package so that the cut pieces may be used as bonding pads.
In Japanese Patent Laid-Open No. 39455/1990, there is disclosed an example of a large-scale integrated circuit such as a gate array or Sea-of gate array, in which a plurality of electrode pads are formed to cause the portions cut at predetermined positions to act as individually independent supply patterns so that the power may be fed to the necessary circuits only.
In Japanese Patent Laid-Open No. 60188/1978, there is disclosed an example of an integrated circuit having composite functions to make it possible to control the power supply for each function thereby to reduce the power consumption by providing power supply lines separately for the individual functions inside of an integrated circuit.